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1 wide v in dual standard buck regulator with 3a/3a continuous output current isl78208 the isl78208 is a dual standard buck regulator capable of 3a per channel with continuous output current. with an input range of 4.5v to 28v, it provides a high frequency power solution for a variety of point of load applications. the pwm controller in the is l78208 drives an internal switching n-channel power mosfet and requires an external schottky diode to generate the ou tput voltage. the integrated power switch is optimized for excellent thermal performance up to 3a of output current. the pwm regulator switches at a default frequency of 500khz and it can be user programmed or synchronized from 300khz to 2mhz. the isl78208 utilizes peak current mode control to provide flexibility in component selection and minimize solution size. the protection features include overcurrent, uvlo and thermal overload protection. the isl78208 is available in 5mm x 5mm 32 lead wettable flank quad flat pb-f ree (wfqfn) package. the isl78208 is both aec - q100 rated and fully ts16949 compliant. the isl78208 is rated for the automotive temperature range (-40c to +105c). features ? wide input voltage range from 4.5v to 28v ? adjustable output voltage with continuous output current up to 3a ? current mode control ? adjustable switching freque ncy from 300khz to 2mhz ? independent power-good detection ? selectable in-phase or out-of-phase pwm operation ? independent, sequential, ratiom etric or absolute tracking between outputs ? internal 2ms soft-start time ? overcurrent/short circuit protection, thermal overload protection, uvlo ? boot undervoltage detection ? ts16949 compliant ? aec - q100 tested ? pb-free (rohs compliant) applications ? dsp and embedded processor power supply ? infotainment system power figure 1. efficiency vs load, v in = 28v, t a = +25c 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 12v out 1mhz july 12, 2013 fn8354.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl78208 2 fn8354.0 july 12, 2013 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 typical application schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operation initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on reset and undervoltage lockout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output tracking and sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 protection features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 buck regulator overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 boot undervoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 application guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 synchronization control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 buck regulator output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 current sharing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 theory of compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 pwm comparator gain fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power stage transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 rectifier selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power derating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
isl78208 3 fn8354.0 july 12, 2013 pin configuration isl78208 (32 ld wfqfn) top view vin1 phase1 pgood1 fs pgnd2 nc5 boot2 3 4 5 6 21 20 19 18 31 30 29 28 9101112 sgnd pgnd1 nc1 vcc phase1 phase2 en1 13 22 32 en2 boot1 phase2 nc3 vin2 fb2 ss2 23 27 26 syncout 1 2 fb1 ss1 comp1 syncin pgood2 15 vin1 14 24 pd 25 comp2 7 vin2 16 17 nc4 8 nc2 pin descriptions pin number symbol pin description 25, 32 comp2, comp1 comp1/comp2 is the output of the error amplifier. 1, 24 fb1, fb2 feedback pin for the regulator. fb is the negative input to the voltage loop error amplifier. comp is the output of the error amplifier. the output voltage is set by an external resistor divider connected to fb. in addition, the pwm regulator?s power-good and undervoltage protection circuits use fb1/2 to monitor the regulator output voltage. 2, 23 ss1, ss2 soft-start pins for each controller. the ss1/2 pi ns control the soft-start and sequence of their respective outputs. a single capacitor from the ss pin to grou nd determines the output ramp rate. see the ?output tracking and sequencing? on page 15 for soft-start and output tracking/sequencing details. if ss pins are tied to vcc, an internal soft-start of 2ms will be used. maximum c ss value is 50nf. 3, 22 pgnd1, pgnd2 power ground connections. connect directly to the system gnd plane. 5, 20 boot1, boot2 floating bootstrap supply pin for the power mosfet gate driver. the bootstrap capacitor provides the necessary charge to turn on the internal n-channel mosfet. connect an external capacitor from this pin to phase. 6, 7, 18, 19 phase1, phase2 switch node output. it connects the so urce of the internal power mosfet with the external output indu ctor and with the cathode of the external diode. 9, 10, 15, 16 vin1, vin2 the input supply for the power stage of th e pwm regulator and the source for the internal linear regulat or that provides bias for the ic. place a minimum of 10f ceramic capacitance from each vin to gnd and close to the ic for decoupling. 11, 13 en1, en2 pwm controller?s enable inputs. the pwm controllers are held off when the pin is pulled to ground. when the voltage on this pin rises above 2v, the pwm controlle r is enabled. if en1, en 2 pins are driven by an external signal, the minimum off-time for en1, en2 should be: where c ss is the soft-start pin capacitor (nf). isl78208 do es not have debouncing to en1, en2 external signals. en_t_off s () 10 sc ss 2.2nf ? ? =
isl78208 4 fn8354.0 july 12, 2013 12 vcc output of the internal 5v linear regulator. decoup le to pgnd with a minimum of 4.7f ceramic capacitor. this pin is provided only for inte rnal bias of isl78208 (not to be loaded with current over 10ma). 27 syncout synchronization output. provides a sign al that is the inverse of the syncin signal. 28 syncin connect to an external signal for synchronization from 300khz to 2mhz (negativ e edge trigger). syncin is not allowed to be floating. when syncin = logic 0, phase1 and phase2 are running at 180 out-of-phase. when syncin = logic 1, phase1 and phase2 are running at 0 in-phase. when syncin = an external clock, phase1 and phase2 are running at 180 out-of-phase. external sync frequency applied to the syncin pin sh ould be at least 2.4 times the internal switching frequency setting. 29 sgnd signal ground connections. the exposed pad must be connected to sgnd and soldered to the pcb. all voltage levels are measured with respect to this pin. 4, 8, 14, 17, 21 nc1, nc2, nc3, nc4, nc5 this is a no connection pin. 30 fs frequency selection pin. tie to vcc for 500khz switching frequency. connect a resistor to gnd for adjustable frequency from 300khz to 2mhz. 26, 31 pgood2, pgood1 open drain power-good output that is pulled to ground when the output voltage is below regulation limits or during the soft-start interval. there is an internal 5m ? internal pull-up resistor. epad pd the exposed pad must be connected to the system gnd plane with as many vias as possible for proper electrical and thermal performance. pin descriptions (continued) pin number symbol pin description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL78208ARZ isl7820 8arz -40 to +105 32 ld wfqfn l32.5x5h notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl78208 . for more information on msl please see techbrief tb363 .
isl78208 5 fn8354.0 july 12, 2013 typical application schematics figure 2. dual 3a output (v in range from 4.5v to 28v) figure 3. single 6a output (vin ra nge from 4.5v to 28v) current sharing isl78208 vin1 nc c 2 r 4 comp1 fb1 c 71 en1 r 1 r 2 c 1 v out1 c 9 l1 phase1 boot1 v out1 c 8 68pf 42.2k 470pf 69.8k 8.06k 10nf d 1 7 h b340b 47 f 20 f c 5 r 8 comp2 fb2 r 5 r 6 c 4 v out2 68pf 25.5k 470pf 69.8k 8.06k c 13 l 2 phase2 boot2 c 12 10nf d 2 7 h b340b 47 f en2 3a 3a fs ss1 vcc vin2 ss2 pgood2 pgood1 syncin syncout c 72 10 f vcc vcc vcc v out2 4.7f pgnd1/2 sgnd 30 23 2 26 25 31 18/19 20 32 1 28 27 3/22 13 11 29 12 9/10 15/16 6/7 5 24 4/8/14/17/21 isl78208 vin1 nc comp1 fb1 c 71 en1 c 9 l 1 phase1 boot1 c8 10n f d 1 7 h b340b 47 f 20 f c 5 r 8 comp2 fb2 r 5 r 7 r 6 c 4 v out1 0 68pf 42.2k 1nf 34k 8.06k c 13 phase2 boot2 c 12 10nf d 2 7 h b340b 47 f en2 6a fs ss1 vcc vin2 ss2 pgood2 pgood1 syncin syncout c72 10 f vcc 4.7f v out1 v out1 fb2 comp2 fb2 pgnd1/2 sgnd 25 24 32 1 9/10 15/16 30 23 2 26 31 18/19 20 28 27 3/22 13 11 29 12 6/7 5 l 2 c ss2 47nf c ss1 47nf 4/8/14/17/21
isl78208 6 fn8354.0 july 12, 2013 functional block diagram slope comp oscillator ldo 0.8v csa2 ea reference + - comp2 + - vin1 control soft-start monitor voltage fs fault monitor power-on reset monitor thermal monitor +150c epad gnd csa2 + comp2 v cc = 5v gate drive boot uv + - -10% vcc 5m ? boot2 csa2 gate drive boot uv detection boot refresh control ea 0.8v + - + - control soft-start monitor voltage csa1 monitor fault csa1 + comp1 + - -10% vcc 5m ? phase1 pgood1 boot1 fb1 en1 en2 phase2 vin2 fb2 comp1 vin1 pgood2 pgnd2 pgnd1 syncout syncin csa1 boot refresh control slope comp ss2 ss1 sgnd vcc vcc vcc vin1 reference detection
isl78208 7 fn8354.0 july 12, 2013 absolute maximum rating s thermal information vin1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +30v phase1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +30v boot1/2 to phase1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v fs to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v syncin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v fb1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.95v en1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v pgood1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v comp1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v vcc to gnd short maximum duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s syncout to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v ss1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 4kv charged device model (tested per jesd22-c101e). . . . . . . . . . . . .2.2kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 300v latch up (tested per jesd-78a; class 2, le vel a) . . . . . . . . . . . . . . 100ma thermal resistance ja (c/w) jc (c/w) wfqfn package (notes 4, 5) . . . . . . . . . . . 30 1.5 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c operating temperature range . . . . . . . . . . . . . . . . . . . . . .-40c to +105c recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 28v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t a = -40c to +105c, v in = 4.5v to 28v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c parameter symbol test conditions min (note 8) typ max (note 8) units supply voltage v in voltage range v in 4.5 28 v v in quiescent supply current i q 1.2 2.2 ma v in shutdown supply current i sd en1/2 = 0v 20 45 a v cc voltage v cc v in = 12v; i out = 0ma 4.5 5.1 5.6 v power-on reset v in por threshold rising edge 3.9 4.4 v falling edge 3.2 3.7 v oscillator nominal switching frequency f sw fs = vcc 420 500 580 khz resistor from fs to gnd = 383k ? 300 khz resistor from fs to gnd = 40.2k ? 2000 khz fs voltage v fs fs = 100k ? 780 800 820 mv switching frequency syncin = 600khz 300 khz 1.2mhz syncin 4mhz, +25c 600 2000 khz 1.2mhz syncin 4mhz, -40c to +105c 600 1500 minimum off-time t off 130 ns error amplifier error amplifier transconductance gain gm 125 205 285 a/v fb1, fb2 leakage current vfb = 0.8v 10 100 na current sense amplifier gain r t 0.18 0.21 0.24 v/a reference voltage 0.792 0.8 0.808 v
isl78208 8 fn8354.0 july 12, 2013 soft-start ramp time ss1/2 = vcc 1.5 2.5 3.5 ms soft-start charging current i ss 1.4 2 2.6 a power-good pg1, pg2 trip level pg to pgood1, pgood2 rise 91 94 % fall 82.5 85.5 % pg1, pg2 propagation delay percent age of the soft-start time 10 % pg1, pg2 low voltage isink = 3ma 100 300 mv enable input en1, en2 leakage current en1/2 = 0v/5v -1 1 a en1, en2 input threshold voltage low level 0.8 v float level 1.0 1.4 v high level 2 v sync input/output syncin input threshold falling edge 1.1 1.4 v rising edge 1.6 1.9 v hysteresis 200 mv syncin leakage current syncin = 0v/5v 10 1000 na syncin pulse width 100 ns syncout phase-shift to syncin measured from rising edge to rising edge, if duty cycle is 50% 180 syncout frequency range t a = +25c 600 4000 khz t a = -40c to +105c 600 3000 syncout output voltage high isyncout = 3ma v cc - 0.3 v cc -0.08 v syncout output voltage low 0.08 0.3 v fault protection thermal shutdown temperature t sd rising threshold 150 c t hys hysteresis 20 c overcurrent protection threshold (note 7) 4.1 5.1 6.1 a ocp blanking time 60 ns power mosfet highside r hds i phase = 100ma 75 150 m ? internal boot1, boot2 refresh lowside r lds i phase = 100ma 1 ? phase leakage current en1/2 = phase1/2 = 0v 300 na phase rise time t rise v in = 25v 10 ns notes: 6. test condition: v in = 28v, fb forced above regulation point (0.8v), no switch ing, and power mosfet gate charging current not included. 7. established by both current sense amplifier gain test and current sense amplifier output test @ i l = 0a. 8. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications t a = -40c to +105c, v in = 4.5v to 28v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl78208 9 fn8354.0 july 12, 2013 typical performance curves circuit of figure 2. v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. figure 4. efficiency vs load, t a = +25c, v in = 28v figure 5. efficiency vs load, t a = +25c, f sw = 500khz, v in =12v figure 6. efficiency vs load, t a = +25c, current sharing 5v out , f sw = 500khz figure 7. power dissipation vs load, t a = +25c, current sharing 5v out , f sw = 500khz figure 8. power dissipation vs load, t a = +85c, current sharing 5v out , f sw = 500khz figure 9. v out regulation vs load, channel 1, t a = +25c, 5v out , f sw = 500khz 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 3.3v out 500khz 9v out 1mhz 12v out 1mhz 1.8v out 300khz 5v out 500khz 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 3.3v out 5v out 40 50 60 70 80 90 100 0123456 output load (a) efficiency (%) 12v in 9v in 28v in 0.0 0.7 1.4 2.1 2.8 3.5 4.2 output load (a) power dissipation (w) 0123456 12v in 9v in 28v in 0.0 0.8 1.6 2.4 3.2 4.0 4.8 output load (a) power dissipation (w) 0123456 12v in 9v in 28v in 4.98 4.99 5.00 5.01 5.02 5.03 5.04 0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) output voltage (v) 12v in 9v in 28v in
isl78208 10 fn8354.0 july 12, 2013 figure 10. v out regulation vs load, current sharing, t a = +25c, 5v out , f sw = 500khz figure 11. v out regulation vs load, channel 2, t a = +25c, 3.3v out , f sw = 500khz figure 12. output voltage regulation vs v in , channel 1, t a = +25c, 5v out , f sw = 500khz figure 13. output voltage regulation vs v in , current sharing, t a = +25c, 5v out , f sw = 500khz figure 14. output voltage regulation vs v in , channel 2, t a = +25c, 3.3v out , f sw = 500khz figure 15. steady state operation at no load channel 1 typical performance curves circuit of figure 2. v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. (continued) 4.98 4.99 5.00 5.01 5.02 5.03 5.04 output load (a) output voltage (v) 12v in 9v in 28v in 0123456 3.320 3.322 3.323 3.325 3.326 3.328 3.329 0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) output voltage (v) 18v in 12v in 28v in 4.98 4.99 5.00 5.01 5.02 5.03 5.04 0 5 10 15 20 25 30 input voltage (v) output voltage (v) 0a 2a 3a 4.96 4.97 4.98 4.99 5.00 5.01 5.02 0 5 10 15 20 25 30 input voltage (v) output voltage (v) 0a 4a 6a 3.310 3.315 3.320 3.325 3.330 3.335 3.340 0 5 10 15 20 25 30 input voltage (v) output voltage (v) 0a 2a 3a lx1 5v/div v out1 ripple 20mv/div il1 0.1a/div
isl78208 11 fn8354.0 july 12, 2013 figure 16. steady state operation at no load channel 1 (v in = 9v) figure 17. steady state operation at no load channel 2 figure 18. steady state operation with full load channel 1 f igure 19. steady state operatio n with full load channel 2 figure 20. steady state operation with full load current sharing figure 21. load transient channel 1 typical performance curves circuit of figure 2. v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. (continued) lx1 5v/div v out1 ripple 20mv/div il1 0.2a/div lx2 5v/div v out2 ripple 20mv/div il2 0.1a/div lx1 5v/div v out1 ripple 20mv/div il1 1a/div lx2 5v/div v out2 ripple 20mv/div il2 1a/div lx2 10v/div v out ripple 20mv/div lx1 10v/div v out1 ripple 20mv/div il1 2a/div
isl78208 12 fn8354.0 july 12, 2013 figure 22. load transient channel 2 figure 23. soft-start with no load channel 1 figure 24. soft-start with no load channel 2 figure 25. soft-start at full load channel 1 figure 26. soft-start at full load channel 2 figure 27. shutdown with no load channel 1 typical performance curves circuit of figure 2. v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. (continued) v out2 ripple 20mv/div il2 2a/div en1 5v/div v out1 2v/div il1 0.5a/div pg1 5v/div en2 5v/div v out2 2v/div il2 0.5a/div pg2 5v/div en1 5v/div v out1 2v/div il1 2a/div pg1 5v/div en2 5v/div v out2 2v/div il2 2a/div pg2 5v/div en1 5v/div v out1 1v/div il1 0.5a/div pg 5v/div il1 0.5a/div
isl78208 13 fn8354.0 july 12, 2013 figure 28. shutdown with no load channel 2 figur e 29. independent start-up sequencing at no load figure 30. ratiometric start-up sequencing at no load figure 31. absolute start-up sequencing at no load figure 32. steady state operation channel 1 at full load with sync frequency = 4mhz figure 33. steady state operation channel 2 at full load with sync frequency = 4mhz typical performance curves circuit of figure 2. v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. (continued) en2 5v/div v out2 0.5v/div il2 0.5a/div pg 5v/div en1, 2, 5v/div v out2 2v/div v out1 2v/div en1, 2, 5v/div v out2 2v/div v out1 2v/div v out2 2v/div v out1 2v/div en1, 2, 5v/div lx1 10v/div v out1 ripple 20mv/div lx2 10v/div sync 5v/div lx1 10v/div v out2 ripple 20mv/div lx2 10v/div sync 5v/div
isl78208 14 fn8354.0 july 12, 2013 figure 34. output short circuit channel 1 figure 35. output short circuit hiccup and recovery for channel 1 figure 36. output short circuit channel 2 figure 37 . output short circuit hiccup and recovery for channel 2 typical performance curves circuit of figure 2. v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. (continued) v out1 2v/div phase1 10v/div il1 2a/div pg1 5v/div v out1 2v/div phase1 10v/div il1 2a/div pg1 5v/div v out2 2v/div phase2 10v/div il2 2a/div pg2 5v/div v out2 2v/div phase2 10v/div il2 2a/div pg2 5v/div
isl78208 15 fn8354.0 july 12, 2013 detailed description the isl78208 combines a standard buck pwm controller with an integrated switching mosfet. the buck controller drives an internal n-channel mosfet and re quires an external diode to deliver load current up to 3a. a schottky diode is recommended for improved efficiency and performance over a standard diode. the standard buck regulator can operate from an unregulated dc source, such as a battery, with a voltage ranging from +4.5v to +28v. the converter output can be regulated to as low as 0.8v. these features make the isl78208 ideally suited for infotainment system power, and dsp and embedded processor power supply applications. the isl78208 employs a peak curr ent mode control loop which simplifies feedback loop compensation and rejects input voltage variation. external feedback loop compensation allows flexibility in output filter component selection. the regulator switches at a default 500khz and it can be adjusted from 300khz to 2mhz with a resistor from fs to gnd. the isl78208 is also synchronizable from 300khz to 2mhz. operation initialization the power-on reset circuitry and enable inputs prevent false start-up of the pwm regulator outp ut. once all input criteria are met, the controller soft-starts the output voltage to the programmed level. power-on reset and undervoltage lockout the isl78208 automatically initializes upon receipt of input power supply. the power-on reset (por) function continually monitors vin1 voltage. while below the por threshold, the controller inhibits switching of the internal power mosfet. once exceeded, the controller initializes the internal soft-start circuitry. if vin1 supply drops below their falling por threshold during soft-start or operation, the buck regulator is disabled until the input voltage returns. enable and disable when en1 and en2 are pulled low, the device enters shutdown mode and the supply current drops to a typical value of 20a. all internal power devices are held in a high-impedance state while in shutdown mode. the en pin enables the controll er of the isl78208. when the voltage on the en pin exceeds it s logic rising threshold, the controller initiates the 2ms soft-start function for the pwm regulator. if the voltage on th e en pin drops below the falling threshold, the buck regulator shuts down. if en1, en2 pins are driven by an external signal, the minimum off-time for en1, en2 should be: where c ss is the soft-start pin capacitor (nf). isl78208 does not have debouncing to en1, en2 external signals. power-good pg is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage via the fb pin. pg is actively held low when en is low and during the buck regulator soft-start period. after the soft-start period terminates, pg becomes high impedance as long as the output voltage (monitored on the fb pin) is ab ove 90% of the nominal regulation voltage set by fb. when v out drops 10% below the nominal regulation voltage, the isl78208 pulls pg low. any fault condition forces pg low until the fault cond ition is cleared by attempts to soft-start. there is an internal 5m internal pull-up resistor. output voltage selection the regulator output voltages is easily programmed using an external resistor divider to scale v out relative to the internal reference voltage. the scaled voltage is applied to the inverting input of the error amplifier; refer to figure 38. the output voltage programming resistor, r 2 , depends on the value chosen for the feedback resistor, r 3 , and the desired output voltage, v out , of the regulator. equation 2 describes the relationship between v out and resistor values. r 3 is often chosen to be in the 1k ? to 10k ? range. if the desired output voltage is 0.8v, then r 3 is left unpopulated and r 2 is 0 ? . output tracking and sequencing output tracking and sequenci ng between channels can be implemented by using the ss1 and ss2 pins. figures 39, 40 and 41 show several configurations for output tracking/sequencing for a 5.0v and 3.3v application. independent soft-start for each channel is shown in figure 39 and measured in figure 29. the output ramp-time for each channel (t ss ) is set by the soft-start capacitor (c ss ). maximum c ss value is 50nf. ratiometric tracking is achieved in figure 40 by using the same value for the soft-start capacitor on each channel; it is measured in figure 30. by connecting a feedback network from v out1 to the ss2 pin with the same ratio that sets v out2 voltage, absolute tracking shown in figure 41 is implemented. the measurement is shown in figure 31. if the output of ch annel 1 is shorted to gnd, it will enter overcurrent hiccup mode, ss2 will be pulled low through the added resistor between v out1 and ss2 and this will force channel 2 into hiccup as well. if the output of channel 2 is shorted to gnd with vout1 in regulation, it will enter overcurrent en_t_off s () 10 sc ss 2.2nf ? ? = (eq. 1) r 2 v out ( 0.8 ) r 3 0.8 ? ? ? = (eq. 2) r 2 r 3 0.8v ea reference + - v out figure 38. external resistor divider fb c ss f [] 2.5*t ss s () = (eq. 3)
isl78208 16 fn8354.0 july 12, 2013 hiccup mode with a very short hiccup waiting time. the reason is that vout1 is still in regulation and can pull-up ss2 very quickly via the resistor added between vout1 and ss2. figure 42 illustrates output se quencing. when en1 is high and en2 is floating, out1 comes up first and out2 won't start until out1 > 90% of its regulation point. if en1 is floating and en2 is high, out2 comes up first and out1 won't start until out2 > 90% of its regulation point. if en1 = en2 = high, out1 and out2 come up at the same time. please refer to table 1 for conditions related to figure 42 (output sequencing). protection features the isl78208 limits th e current in all on-c hip power devices. overcurrent protection limits the current on the two buck regulators and internal ldo for v cc . buck regulator overcurrent protection during the pwm on-time, the current through the internal switching mosfet is sampled and scaled through an internal pilot device. the sampled current is compared to a nominal 5a overcurrent limit. if the sampled current exceeds the overcurrent limit reference level, an internal overcurrent fault counter is set to 1 and an internal flag is set. the internal power mosfet is immediately turned off and will not be turned on again until the next switching cycle. the protection circuitry continues to monitor the current and turns off the internal mosfet as described. if the overcurrent condition persists for 17 sequential clock cycles, the overcurrent fault counter overflows indicating an overcurrent fault condition exists. the regulator is shut down and power-good goes low. the buck controller attempts to recover from the overcurrent condition after waiting 8 soft -start cycles. the internal overcurrent flag and counter are re set. a normal soft-start cycle is attempted and normal oper ation continues if the fault condition has cleared. if the ov ercurrent fault counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats. table 1. output sequencing en1 en2 v out1 v out2 note high floating first after v out1 >90% floating high after v out2 > 90% first high high same time as v out2 same time as v out1 floating floating not allowed ss2 ss1 v out1 c2 10nf c 3 c 4 v out2 isl78208 5.0v 3.3v figure 39. independent start-up vcc ss2 ss1 v out1 c 3 c 4 v out2 isl78208 5.0v 3.3v figure 40. ratiometric start-up vcc vcc ss2 ss1 v out1 c 3 c 4 v out2 r 2 8.06k r 1 25.5k 5.0v 3.3v figure 41. absolute start-up isl78208 vcc ss2 ss1 v out1 c 3 c 4 v out2 5.0v 3.3v en1 en2 figure 42. output sequencing isl78208 vcc vcc
isl78208 17 fn8354.0 july 12, 2013 thermal overload protection thermal overload protection limits maximum junction temperature in the isl78208. when the junction temperature (t j ) exceeds +150c, a thermal sensor sends a signal to the fault monitor. the fault monitor commands the buck regulator to shut down. when the junction temperature has decreased by 20c, the regulator will attempt a normal soft-start sequence and return to normal operation. for continuous operation, the +125c junction temperature rating should not be exceeded. boot undervoltage protection if the boot capacitor voltage falls below 2.5v, the boot undervoltage protection circuit will pull the phase pin low through a 1 ? switch for 400ns to recharge the capacitor. this operation may arise during long periods of no switching as in no load situations. application guidelines operating frequency the isl78208 operates at a de fault switching frequency of 500khz if fs is tied to vcc. ti e a resistor from fs to gnd to program the switching frequency from 300khz to 2mhz, as shown in equation 4. where: t is the switching period in s. synchronization control the frequency of operation can be synchronized up to 2mhz by an external signal applied to the syncin pin. the falling edge on the syncin triggers the rising edge of phase1/2. the switching frequency for each output is half of the syncin frequency. output inductor selection the inductor value determines the converter?s ripple current. choosing an inductor current re quires a somewhat arbitrary choice of ripple current, i. a reasonable starting point is 30% of total load current. the inductor value can then be calculated using equation 5: increasing the value of inductance reduces the ripple current and thus ripple voltage. however, the larger inductance value may reduce the converter?s response time to a load transient. the inductor current rating should be such that it will not saturate in overcurrent conditions. buck regulator output capacitor selection an output capacitor is required to filter the inductor current. output ripple voltage and transien t response are 2 critical factors when considering output capacitance choice. the current mode control loop allows the usage of low esr ceramic capacitors and thus smaller board layout. electr olytic and polymer capacitors may also be used. additional consideration applies to ceramic capacitors. while they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter applic ation, these cond itions do not reflect reality. as a result, the actual capacitance may be considerably lower than the advertised value. consult the manufacturers data sheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so that this effect can be eas ily accommodated. the effects of ac voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. the result of these considerations can easily result in an effective capacitance 50% lower than the rated value. nonetheless, they are a very good choice in many applications due to their reliability and extremely low esr. the following equations allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr): where i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: regarding transient response needs, a good starting point is to determine the allowable overshoot in v out if the load is suddenly removed. in this case, energy stored in the inductor will be transferred to c out causing its voltage to rise. after calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. equation 8 determines the r fs k [] 122k ? t ( 0.17 s ) ? = (eq. 4) figure 43. r fs selection vs fs 300 200 100 0 500 750 1000 1250 1500 1750 2000 fs (khz) r fs (k ? ) (eq. 5) l v in v out ? fs i ------------------------------- - v out v in --------------- - = v outripple i 8 ? f sw ? c out -------------------------------------- - = (eq. 6) v outripple i*esr = (eq. 7)
isl78208 18 fn8354.0 july 12, 2013 required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where v outmax /v out is the relative maximum overshoot allowed during the removal of the load. for an overshoot of 5%, the equation becomes equation 9: the graph in figure 44 show s the relationship of c out and % overshoot at 3 different output voltages. l is assumed to be 7h and i out is 3a. current sharing configuration in current sharing configuration, fb1 is connected to fb2, en1 to en2, comp1 to comp2 and v out1 to v out2 as shown in figure 3. as a result, the equivalent gm doubles its single channel value. since the two channels are out-of-phase, the frequency will be 2x the channel switching frequency. ripple current cancellation will reduce the ripple current seen by the output capacitors and thus lower the ripple voltage. this results in the ability to use less capacitance than would be required by a single phase design of similar rating. ripple current cancellation also reduces the ripple current seen at the input capacitors. input capacitor selection to reduce the resulting input voltage ripple and to minimize emi by forcing the very high frequency switching current into a tight local loop, an input capacitor is required. the input capacitor must have adequate ripple current rating, which can be approximated by the equation 10. if capacitors other than mlcc are used, attention must be paid to ripple and surge current ratings. where d = v o /v in the input ripple current is graphically represented in figure 45. a minimum of 10f ceramic capaci tance is required on each vin pin. the capacitors must be as close to the ic as physically possible. additional capacitance may be used. loop compensation design isl78208 uses a constant freq uency current mode control architecture to achieve simplifi ed loop compensation and fast loop transient response. the compensator schematic is shown in figure 47. as mentioned in the c out selection, isl78208 allows the usage of low esr output capacitor. choice of the loop bandwidth f c is somewhat arbitrary but should not exceed 1/4 of the switching frequency. as a starting point, the lower of 100khz or 1/6 of the switching frequency is reasonable. the following equations determine initial component values for the compensation, allowing the designer to make the selection with minimal effort. further detail is provided in ?theory of compensation? on page 19 to allow fine tuning of the compensator. compensation resistor r 1 is given by equation 11: which when applied to isl78208 becomes equation 12: where c o is the output capacitor value [f], f c = loop bandwidth [khz] and v o is the output voltage [v]. compensation capacitors c 1 [nf], c 2 [pf] are given by equation 13: where io [a] is the output load current, r 1 ( ? ) and r c ( ? ) is the esr of the output capacitor c o . example: v o = 5v, i o = 3a, f s = 500khz, f c = 50khz, c o = 47f/r c = 5m ? , then the compensation resistance r 1 = 96k ? . the compensation capacitors are: c 1 = 815pf, c 2 = 2.5pf (there is appr oximately 3pf parasitic capacitance from v comp to gnd; therefore, c 2 is optional). (eq. 8) c out i out 2 * l v out 2 * v outmax v out ? () 2 1 ) ? -------------------------------------------------------------------------------------------- = c out i out 2 * l v out 2 * 1.05 ( 2 1 ) ? ----------------------------------------------------- = (eq. 9) figure 44. c out vs overshoot v outmax /v out v outmax /v out c out (f) 1.02 1.04 1.06 1.08 1.10 80 60 40 20 0 3.3v out 5v out 12v out i rms io ------------ dd 2 ? = (eq. 10) figure 45. i rms /i o vs duty cycle d i rms /i o 0.6 0.5 0.4 0.3 0.2 0.1 0 00.20.40.60.8 r 1 2 f c v o c o r t g m v fb ----------------------------------- = (eq. 11) r 1 k [] 0.008247 ? f c ? v o ? c o = (eq. 12) (eq. 13) c 1 c o v o 10 () 3 i o r 1 ----------------------------------------- c 2 c o r c 10 () 6 r 1 ----------------------------------------- = , =
isl78208 19 fn8354.0 july 12, 2013 theory of compensation the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design. the inductor is not cons idered as a state variable for current mode control and the sy stem becomes a single order system. it is much easier to desi gn a compensator to stabilize the voltage loop than voltage mode control. figure 46 shows the small signal model of the synchronous buck regulator. pwm comparator gain f m the pwm comparator gain f m for peak current mode control is given by equation 14: where s e is the slew rate of the slope compensation and s n is given by equation 15. where: r t is trans-resistance, and is th e product of the current sensing resistance and gain of the curre nt amplifier in current loop. current sampling transfer function h e (s) in current loop, the current sign al is sampled every switching cycle. equation 16 shows the transfer function: where q n and n are given by . power stage transfer functions transfer function f 1 (s) from control to output voltage is calculated in equation 17: where transfer function f 2 (s) from control to inductor current is given by equation 18: where . current loop gain t i (s) is expressed as equation 19: the voltage loop gain with open current loop is calculated in equation 20: the voltage loop gain with curre nt loop closed is given by equation 21: where is the feedback voltage of the voltage error amplifier. if t i (s)>>1, then equation 21 can be simplified as shown in equation 22: from equation 22, it is shown that the system is a single order system, which has a single pole located at before the half switching frequency. therefore, a simple type ii compensator can be easily used to stabilize the system. d i l i in l + 1:d + l i co rc ro -av(s) d v comp fm he(s) + t k v o t(s) i l + 1:d + co rc ro -av(s) r t fm he(s) t i (s) t v (s) ^ v in ^ ^ ^ ^ figure 46. small signal mo del of synchronous buck regulator ^ ^ v in d ^ f m d ? v ? comp ---------------- - 1 s e s n + () t s -------------------------------- == (eq. 14) s n r t v in v o ? l --------------------- = (eq. 15) h e s () s 2 n 2 ------ - = s n q n --------------- 1 ++ (eq. 16) q n 2 -- - ? = n f s = = , f 1 s () v ? o d ? ------ v in 1 s esr ----------- - + s 2 o 2 ------ - s o q p --------------- 1 ++ -------------------------------------- - == (eq. 17) esr 1 r c c o -------------- - q p r o c o l ------ - o 1 lc o -------------- - = , , = f 2 s () i ? o d ? ---- v in r o r l + -------------------- - 1 s z ------ + s 2 o 2 ------ - s o q p --------------- 1 ++ -------------------------------------- - == (eq. 18) z 1 r o c o -------------- - = t i s () r t f m f 2 s () h e s () = (eq. 19) t v s () kf m f 1 s () a v s () = (eq. 20) l v s () t v s () 1t i s () + ----------------------- - = (eq. 21) k v fb v o ---------- - v fb , = l v s () v fb v o ---------- - r o r l + r t -------------------- - 1 s esr ----------- - + 1 s p ------ - + --------------------- - a v s () h e s () ---------------- p 1 r o c o -------------- - , = (eq. 22) p
isl78208 20 fn8354.0 july 12, 2013 figure 47 shows the type ii compensator and its transfer function is expressed as equation 23: where: the compensator design goal is: high dc gain loop bandwidth f c : gain margin: >10db phase margin: 40 the compensator design proced ure is shown in equation 25: put one compensator pole at zero frequency to achieve high dc gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower. the loop gain t v (s) at crossover frequency of f c has unity gain. therefore, the compensator resistance r 1 is determined by equation 26: where g m is the trans-conductance of the voltage error amplifier, typically 200a/v. compensator capacitor c 1 is then given by equation 27: example: v in = 12v, v o = 5v, i o = 3a, f s = 500khz, c o = 220f/5m , l = 5.6h, g m = 200s, r t = 0.21, v fb =0.8v, s e = 1.1 10 5 v/s, s n =3.4 10 5 v/s, f c = 80khz, then compensator resistance r 1 = 72k . put the compensator zero at 6.6khz (~1.5x c o r o ), and put the compensator pole at esr zero, which is 1.45mhz. the compensator capacitors are: c 1 = 470pf, c 2 = 3pf (there is appr oximately 3pf parasitic capacitance from v comp to gnd; therefore, c 2 is optional). figure 48a shows the simulated voltage loop gain. it is shown that it has 80khz loop bandwidth with 69 phase margin and 15db gain margin. optional addition phase boost can be added to the overall loop response by using c 3 . rectifier selection current circulates from ground to the junction of the external schottky diode and the inductor when the high-side switch is off. as a consequence, the polarity of the switching node is negative with respect to ground. this vo ltage is approximately -0.5v (a schottky diode drop) during the off-time. the rectifier's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. the power dissipation when the schottky diode conducts is expressed in equation 28: where: v d is the voltage drop of the schottky diode. selection of the schottky diode is critical in terms of the high temperature reverse bias leakage current which is very dependent on vin and - + r 1 v ref v fb vo gm v comp c 2 - + c 1 v ref v fb vo v comp figure 47. type ii compensator c 3 r 2 r 3 a v s () v ? comp v ? fb ---------------- - g m c 1 c 2 + -------------------- - 1 s cz1 ------------ - + ?? ?? 1 s cz2 ------------ - + ?? ?? s1 s cp --------- - + ?? ?? --------------------------------------------------------- = = (eq. 23) cz1 1 r 1 c 1 -------------- - cz2 1 r 2 c 3 -------------- - = cp , c 1 c 2 + r 1 c 1 c 2 ---------------------- - = , = (eq. 24) 1 4 -- - to 1 10 ------ ?? ?? f s (eq. 25) put compensator zero cz1 1to3 () 1 r o c o ----------------- = r 1 2 f c v o c o r t g m v fb ----------------------------------- = (eq. 26) c 1 1 r 1 cz ----------------- c 2 1 2 r 1 f esr ------------------------ - = , = (eq. 27) 100 1?10 3 1?10 4 1?10 5 1?10 6 -30 -15 0 15 30 45 60 gain (db) figure 48a. -20 0 20 40 60 80 100 phase () 100 1?10 3 1?10 4 1?10 5 1?10 6 figure 48b. p d w [] i out v d 1 v out v in --------------- - ? ?? ?? ?? ?? = (eq. 28)
isl78208 21 fn8354.0 july 12, 2013 exponentially increasing with temp erature. due to the nature of reverse bias leakage vs temper ature, the diode should be carefully selected to operate in the worst case circuit conditions. catastrophic failure is possible if the diode chosen experiences thermal runaway at elevated temperatures. please refer to application note for diode selection. power derating characteristics to prevent the isl78208 from exceeding the maximum junction temperature, some thermal analysis is required. the temperature rise is given by equation 29: where pd is the power dissipated by the regulator and ja is the thermal resistance from the junc tion of the die to the ambient temperature. the junction temperature, t j , is given by equation 30: where t a is the ambient temperature. for the wfqfn package, the ja is +30c/w. the actual junction temperature should not exceed the absolute maximum junction temperature of +125c. when considering the thermal design, remember to consider the thermal needs of the rectifier diode. the isl78208 delivers full current at ambient temperatures up to +105c if the thermal impedance from the thermal pad maintains the junction temperat ure below the thermal shutdown level, depending on the input voltage/output voltage combination and the switching frequency. the device power dissipation must be reduced to maintain the junction temperature at or below th e thermal shutdown level. layout considerations layout is very important in high frequency switching converter design. with power devices swit ching efficiently between 100khz and 600khz, the resulting current tr ansitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimizes these voltage spikes. as an example, consider the turn-off transition of the upper mosfet. prior to turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is picked up by the schottky diode. any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. careful co mponent selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. there are two sets of critical components in the isl78208 switching converter. the switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. next, are the small signal components, which connect to sensitive nodes or supply critical bypass current and signal coupling. a multi-layer printed circuit board is recommended. figure 49 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component gr ound connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminals to the output inductor short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. in order to dissipate heat generated by the internal ldo and mosfet, the ground pad should be connected to the internal ground plane through at least four vias. this allows the heat to move away from the ic and also ties the pad to the ground plane through a low impedance path. the switching compon ents should be placed close to the isl78208 first. minimize the leng th of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible. position the output inductor and output capacitors between the upper and schottky diode and the load. the critical small signal components include any bypass capacitors, feedback components, and compensation components. place the pwm converter compensation components close to the fb and comp pins. the feedback resistors should be located as close as possible to the fb pin with vias tied straight to the ground plane as required. t rise pd () ja () = (eq. 29) t j t a t rise + () = (eq. 30)
isl78208 22 fn8354.0 july 12, 2013 figure 49. printed circuit board power planes and islands d1 cout1 fb2 cboot vin1 vout1 fb1 comp1 comp2 l2 lx2 trace cin1 cin2 cout2 vout2 d2 cboot vout2 vin2 lx1 trace l1 isl78208 ... . . vias . . .
isl78208 23 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8354.0 july 12, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 12, 2013 fn8354.0 initial release
isl78208 24 fn8354.0 july 12, 2013 package outline drawing l32.5x5h 32 lead quad flat no-lead plastic package (punch qfn with wetable flank) rev 0, 4/12 bottom view detail "a" side view typical recommended land pattern top view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the plated terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: 0.10 b a m c 4 5 pin 1 index area see detail "a" 0.50 0.00 min 0.10 0.05 0.08 c seating plane 0 - 12 c see detail "x" 0.85 0.05 0.05 max 0.25 0.05 0.15 0.05 0.15 0.10 0.40 0.10 2x 2x c a 0.10 c b 0.10 0.50 dia. 1 3 2 a b 4.75 n 0.10 2x 0.10 2x b c a c n 0.50 1 2 3 0.250.05 0.05 0.10 m m b a c c 3.3 pin#1 id r0.20 0.45 a c m b 3.3 (0.50) 0.150.10 (0.45) 0.400.10 0.10 a c m b 5.00 4.75 5.00 0.10 4x 0.420.18 4x 0.420.18 (3.30)sq 32x (0.25) 28x (0.50) (4.80)sq 32x (0.60) detail "x" reference document: jedec mo220 6.
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